1. Field of the Invention
The invention relates to a television receiver for receiving a digital television broadcasting which is sent by using a ground wave or a satellite. More particularly, the invention relates to an apparatus for performing various on-screen display on a screen of a television receiver.
2. Description of the Related Art
A satellite digital television broadcasting for broadcasting a digital video signal by using a satellite has been started. The development of a ground wave digital television broadcasting for broadcasting a digital video signal by using a ground wave is being progressed. In the digital television broadcasting, it is expected to provide various services such as high definition television (HDTV) broadcasting, a multichannel broadcasting, multimedia broadcasting, and the like.
FIG. 1 shows an example of a construction of a conventional digital television receiver. In such a receiver, for instance, a digital video signal is compressed by an MPEG (Moving Picture Experts Group) 2 system and a digital television broadcasting which is broadcasted by a ground wave is received.
According to the MPEG2 system, a video signal is compression encoded by a motion compensation predictive coding and a DCT (Discrete Cosine Transform). In the MPEG2 system, three kinds of picture planes called an I (Intra) picture, a P (Predictive) picture, and a B (Bidirectionally Predictive) picture are sent. In the I picture, a DCT coding is performed by using the pixels of the same frame. In the P picture, the DCT coding using the motion compensation prediction is performed with reference to the I picture or P picture which has already been encoded. In the B picture, the DCT coding using the motion compensation prediction is performed with reference to the I picture or P picture before or after the B picture.
In such a digital television broadcasting, there is a possibility that video signals of a plurality of picture planes of different formats are sent. For example, as an image format having a possibility that a video signal is sent by a digital television broadcasting, as shown in FIG. 2, there are image formats as shown in #1 to #4. As shown in FIG. 2, according to the image format #1, a vertical resolution is equal to 1080 dots, a horizontal resolution is equal to 1920 dots, a resolution aspect ratio is equal to 16:9, and an interlace system is used. According to the image format #2, a vertical resolution is equal to 1080 dots, a horizontal resolution is equal to 1440 dots, a resolution aspect ratio is equal to 16:9, and an interlace system is used. According to the image format #3, a vertical resolution is equal to 720 dots, a horizontal resolution is equal to 1280 dots, a resolution aspect ratio is equal to 16:9, and a noninterlace system is used. According to the image format #4, a vertical resolution is equal to 480 dots, a horizontal resolution is equal to 720 dots, a resolution aspect ratio is equal to 13.5:9, and a noninterlace system is used.
In FIG. 1, the digital television broadcasting signal is received by an antenna 111. The reception signal from the antenna 111 is sent to a tuner circuit 112. A channel set signal is supplied from a microprocessor 101 to the tuner circuit 112.
The microprocessor 101 controls a processing system of a whole television receiver. A program ROM 102 to store a program for deciding the operation and a work RAM 103 are provided for the microprocessor 101. A bus 5 led out from the microprocessor 101 is connected to a block of each section.
In the tuner circuit 112, a reception channel is set on the basis of the channel set signal from the microprocessor 101. In the tuner circuit 112, the signal of the selected reception channel is demodulated and a data stream of MPEG2 of the selected channel is outputted from the tuner circuit 112.
An output of the tuner circuit 112 is supplied to a packet extracting circuit 113. Under the control of the microprocessor 101, the packet extracting circuit 113 extracts a video packet and an audio packet of a specific program with reference to a packet identifier (PID) of a packet header.
The video packet from the packet extracting circuit 113 is supplied to a video decoding circuit 114. The audio packet from the packet extracting circuit 113 is supplied to an audio decoding circuit 115.
The video decoding circuit 114 decompresses the video signal compressed by the MPEG2 system and decodes the digital video signal. Component digital video signals of, for example, Y, Cr, and Cb are outputted from the video decoding circuit 114. The component digital video signals are supplied to a mixing circuit 116.
To display the reception channel, a decoding state, and the like into a video picture plane, the mixing circuit 116 mixes the video signal and an OSD (On Screen Display) signal. For the purpose of such a picture plane display, a display source memory 117, a display image forming circuit 118, and an OSD plane memory 119 are prepared.
Patterns of characters and images serving as sources of display picture planes have been held in the display source memory 117. An output of the display source memory 117 is supplied to the display image forming circuit 118. The display image forming circuit 118 forms a display image by using a display source from the display source memory 117. The formed display image is developed into the OSD plane memory 119 and held. The received video signal and the OSD signal from the OSD plane memory 119 are mixed in the mixing circuit 116.
The OSD plane memory 119 stores data of a whole OSD display image to be mixed and displayed onto the video display image. For example, in case of the image format #1, a display image is stored in the memory by a construction of vertical 1080 dots.times.lateral 1920 dots as shown in FIG. 3A.
Since the display image constructed in the OSD plane memory 119 is mixed with the video data at a timing of a dot clock of the video data by the mixing circuit 116, its aspect size is set to the same size as that of the video display image or a size that is a fraction of an integer with respect to the vertical and lateral directions in order to reduce the memory size. FIG. 3B shows a case where the aspect size is set to 1/2 in both of the vertical and lateral directions.
As for the order to read out the display image data from the OSD plane memory 119 to the OSD, it is read out in accordance with the same scanning order as that of the digital video signal. As a scanning order here, there are a noninterlace and an interlace in a manner similar to the video signal.
At the time of the noninterlace display, as shown in FIG. 4A, the video signal is read out while scanning pixel data from the left to the right and from the top to the bottom. In the reading operation in the horizontal direction, a dot clock itself of the video signal or a clock obtained by frequency dividing the clock is used. In the vertical direction, at the time of the interlace display, as shown in FIG. 4B, the video signal is first outputted while scanning the pixel data of even lines from the left to the right and from the top to the bottom. Subsequently, the video signal is outputted while scanning the pixel data of odd lines from the left to the right and from the top to the bottom.
In FIG. 1, a mixture ratio of the video signal and the OSD signal in the mixing circuit 116 is set by the microprocessor 101 by setting a mixture ratio of the digital video signal from the video decoding circuit 114 and the display image data of the OSD from the OSD plane memory 119 to a value .alpha. of 1 or less. As for the mixture ratio, a case of mixing at five steps as shown in, for example, FIG. 5 is considered. In case of a ratio of 100:0 or 0:100, it seems as if they were switched instead of the mixture.
The function to mix by changing the mixture ratio as mentioned above is realized by a circuit as shown in FIG. 6. In FIG. 6, the digital video signal from the video decoding circuit 114 is multiplied by the value .alpha. of a mixture ratio register 153 by an integrator 151 and the resultant signal is inputted to an adder 154. The display image data of the OSD is multiplied by a value (1-.alpha.) from the mixture ratio register 153 by an integrator 152 and the resultant signal is inputted to the adder 154. The adder 154 adds the inputs of the integrators 151 and 152 and generates a digital video signal to which the OSD display image data has been mixed. In this case, by changing the value .alpha. of the mixture ratio register, the mixture ratio can be arbitrarily set.
In FIG. 1, an analog converter 120 converts the digital video signal formed by the mixing circuit 116 into an analog value. Usually, an A/D converter having a precision of 8 bits or 10 bits for each signal of the RGB signal format or the (Y, Cr, Cb) signal format is used.
An output of the mixing circuit 116 is supplied to the analog converter 120. The analog converter 120 converts the digital video signal into an analog video signal. The analog video signal is outputted from an output terminal 121.
The audio packet from the packet extracting circuit 113 is sent to the audio decoding circuit 115. In the audio decoding circuit 115, the audio packet is converted into a digital audio signal. The digital audio signal has a precision of 16 bits or more. An output of the audio decoding circuit 115 is supplied to an analog converter 122. In the analog converter 122, the digital audio signal is converted into an analog audio signal. The analog audio signal is outputted from an output terminal 123.
As mentioned above, in the television receiver for receiving the digital television broadcasting, to display the reception channel, decoding state, and the like into the video picture plane, the video signal and the OSD signal are mixed, and the display of the reception channel, decoding state, and the like is superimposed and displayed on the screen. As mentioned above, when displaying on the screen, a command to display a predetermined picture plane and a command regarding the display position are issued from the microprocessor 101 to the display image forming circuit 118. A command to set a mixture ratio of a video picture plane and a display picture plane is issued from the microprocessor 101 to the mixing circuit 116.
The display image forming circuit 118 forms a display picture plane by using a source of the display source memory 117 in accordance with the designated display image. In this instance, the microprocessor 101 processes each processing operation in accordance with a procedure stored in the program ROM 102, stores the work data in the process into the RAM 103, and executes a series of processes.
As shown in FIG. 2, in the digital television broadcasting, there is a possibility that video signals of a plurality of picture planes of different formats are transmitted. Although there are a plurality of formats of the picture planes which are sent as mentioned above, the number of display patterns in the display source memory 117 is equal to 1 in the conventional television receiver. There is, consequently, a problem that an additional display picture plane to be synthesized is distorted in dependence on the format of the received picture plane.
That is, when there is one display memory 117, to make it possible to use the OSD plane memory 119 in common, in the case where the video data of the image format using a video image of high resolution is mixed to the OSD display image, as shown in FIG. 7, a reading rate from the OSD plane memory 119 is changed in accordance with the video data.
For example, in the display image forming circuit 118, as shown in FIG. 8, a character font of vertical 24 dots.times.lateral 24 dots is combined with bit map data of lateral 600 dots.times.vertical 200 dots, thereby forming an OSD display image of lateral 640 dots.times.vertical 480 dots as a whole.
In case of using the OSD display image in common for the image format #1, as shown in FIG. 7, a reading rate from the OSD plane memory 119 is set to 1/2 in both of the vertical direction and the horizontal direction. In case of using the OSD display image in common for the image format #2, a reading rate from the OSD plane memory 119 is set to 1/2 in both of the vertical direction and the horizontal direction. In case of using the OSD display image in common for the image format #3, a reading rate from the OSD plane memory 119 is set to 1/2 in only the horizontal direction. In case of using the OSD display image in common for the image format #4, a reading rate from the OSD plane memory 119 is not changed.
With the above method, as shown in FIG. 8, when the pattern drawn on the foregoing bit map data is mixed to the video image of the format #4 and is displayed, if such a pattern has been designed so as to be seen like a true circle, in the case where it is mixed to the video images of the formats #1, #2, and #3, cover range of the OSD image for the video image and the aspect ratio of the OSD image when moving onto the television picture plane of the aspect ratio of 16:9 differ. The circle seen as a true circle cannot be seen like a true circle.
FIG. 9 shows an example in which the OSD image of lateral 640 dots.times.vertical 480 dots is converted so that the OSD image of lateral 1280 dots.times.vertical 960 dots is seemingly derived by reducing the reading rate into 1/2 in both of the vertical and lateral directions and the converted OSD image is mixed to the video data of the image format #1. For the video image, the range of the OSD image is narrowed, the aspect ratio of the OSD image changes for the video image, and the circle which is desired to be seen like a true circle is seen as a longitudinal circle.
FIG. 10 shows an example in which the OSD image of lateral 640 dots.times.vertical 480 dots is converted so that the OSD image of lateral 1280 dots.times.vertical 960 dots is seemingly derived by reducing the reading rate into 1/2 in both of the vertical and horizontal directions and the converted OSD image is mixed to the video data of the image format #2. For the video image, the range of the OSD image is slightly narrowed, the aspect ratio of the OSD image slightly changes for the video image, and the circle which is desired to be seen like a true circle is seen as a slightly distorted circle.
FIG. 11 shows an example in which the OSD image of lateral 640 dots.times.vertical 480 dots is converted so that the OSD image of lateral 1280 dots.times.vertical 480 dots is seemingly derived by reducing the reading rate into 1/2 in the horizontal direction and the converted OSD image is mixed to the video data of the image format #3. For the video image, the range of the OSD image in the vertical direction is narrowed, the aspect ratio of the OSD image changes for the video image, and the circle which is desired to be seen like a true circle is seen as a laterally long circle. It will be obviously understood that a point that the aspect ratio of the bit image changes depending on the display video format as mentioned above fundamentally similarly occurs even in the portion of a character font constructed by a bit map in a narrow region.
Even if the reading rate from the OSD plane memory is changed and is used in common for the image format to draw the OSD image data as much as possible as mentioned above, the cover range of the OSD image for the video image changes, the aspect ratio of the display of the OSD image changes, and information to be notified to the user via the OSD image is distorted. The display quality of the OSD image changes depending on each video format and an additional value as a digital television is deteriorated.